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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:48:25 01/15/2010 
-- Design Name: 
-- Module Name:    demo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demo is
	Port(FPGA_Clk : IN std_logic;
		  I2C_Clk : out std_logic;
		  I2C_Data : IN std_logic;
		  LED : OUT std_logic_vector(3 downto 0);
		  SW : IN std_logic_vector(3 downto 0);
		  IMG_Data : IN std_logic_vector(9 downto 0);
		  IMG_PIXEL_Clk : in std_logic;
		  IMG_ROW_Clk : in std_logic;
		  IMG_ROW_Clk_EN : in std_logic;
		  IMG_VSYNC : in std_logic;
		  IMG_RST : in std_logic);
end demo;

architecture Behavioral of demo is
	signal LEDs : std_logic_vector(3 downto 0);
	signal SWs : std_logic_vector(3 downto 0);
	signal counter : std_logic_vector(23 downto 0):=(others=>'0');
	signal cnt : std_logic_vector(3 downto 0):=X"0";
	signal sI2C_Clk : std_logic:='0';
	signal clk_div : std_logic_vector(7 downto 0):=(others=>'0');
begin
	
	LED<=cnt;
	I2C_Clk<='Z';
	
	process(FPGA_Clk)
	begin
		if rising_edge(FPGA_Clk) then
			if counter = X"1312D0" then
				cnt<=cnt + 1;
				counter<=(others=>'0');
			else
			  counter<=counter+1;
			end if;
			if clk_div = X"7C" then
				sI2C_Clk<=not sI2C_Clk;
				clk_div<=(others=>'0');
			else
			  clk_div<=clk_div+1;
			end if;
		end if;
	end process;			

end Behavioral;

